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North Terrace Campus
School of Electrical and Electronic Engineering
Innova 21, Level 3
The University of Adelaide
SA 5005
Australia

Tel: +61 8 8303 5114
Fax: +61 8 8303 4360
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Chip Gallery

Some of CHiPTec's notable integrated circuits are shown below. Click on an image for more details.

 

  • A high-speed delay measurement chip designed by Andrew Beaumont-Smith for Avalon Systems.
  • A. Beaumont-Smith, W. Marwood, C. C. Lim, K. Eshraghian, "Design and implementation of a GaAs systolic floating-point processing element," IEE Proceedings - Computers and Digital Techniques, vol.143, no.5, pp.325-330, Sep 1996, doi: 10.1049/ip-cdt:19960635.
  • A. Beaumont-Smith, J. Tsimbinos, C.C. Lim and W. Marwood, "A VLSI chip implementation of an A/D converter error table compensator," Computer Standards & Interfaces, Volume 23, Issue 2, May 2001, Pages 111-122, ISSN 0920-5489, doi: 10.1016/S0920-5489(01)00064-2.
  • A. Beaumont-Smith and N. Burgess, "A GaAs 32-bit adder," 13th IEEE Symposium on Computer Arithmetic, pp.10-17, 1997
  • A. Beaumont-Smith, N.Burgess, S. Lefrere and C.C. Lim, "Reduced Latency IEEE Floating-Point Standard Adder Architectures," 14th IEEE Symposium on Computer Arithmetic, pp. 35, 1999. (The chip is a double precision floating-point IEEE-754 standard adder. It was implemented in 0.5 um CMOS, measured 1.8 mm^2, had a 3-cycle latency and implemented all rounding modes.)
  • A 32 kbit correlator for a QPSK/BPSK rake receiver using a multiplier-like counter tree. Designed by N. Brine and K. To in 2002 in a 0.18 um process.
  • A 32-bit CORDIC unit for a numerically controlled oscillator used in a multi-channel receiver. The chip was designed by K. To and M. Goss in 2004 in a 0.18 um process. Sklansky adders were used to improve performance. The chip was fabricated but unfortunately no micrographs were ever taken.
  • uEPIC2004, the MicroElectronics Project IC designed as an undergraduate class project and containing a motor unit for an analog clock controller by Andrew Budimir, Sean Correll and Timothy Fosdike as well as various test circuits by Tariq Islam and Woo Ping Tan.
  • A MIPS processor designed by honours students in CHiPTec (Rhys Bowden, Joel Stanley, Robert Moric and Melanie Tan) and undergraduate students from Harvey Mudd College, California. N. Pinckney, T. Barr, M. Dayringer, M. McKnett, N. Jiang, C. Nygaard, J. Stanley, D. Money-Harris and B. Phillips, "A MIPS R2000 Implementation," 45th ACM/IEEE Design Automation Conference (DAC 2008), San Francisco, California, USA, June 2008, pp. 102-107.
  • A CMOS image sensor consisting of a 64x64 array of photodiodes and using a pulse width modulation architecture. The supporting circuits are buried under 6 dummy metal layers so that the only visible feature is the sensor array. This work is related to S. J. Lee, S. J, O. Kavehei, Y. K. Hong, T. W. Cho, Y. You, K. R. Cho and K. Eshraghian, K., "3D System-on-System (SoS) Biomedical Imaging Architecture for Health Care Applications," IEEE Transactions on Biomedical Circuits and Systems, vol. 4, no. 6, pp. 426-436, 2010.
  • A CMOS image sensor consisting of four 64x64 arrays of photodiodes and using variations of a pulse frequency modulation architecture. The supporting circuits are buried under 6 dummy metal layers so that the only visible features are the sensor arrays. This work is related to S. J. Lee, S. J, O. Kavehei, Y. K. Hong, T. W. Cho, Y. You, K. R. Cho and K. Eshraghian, K., "3D System-on-System (SoS) Biomedical Imaging Architecture for Health Care Applications," IEEE Transactions on Biomedical Circuits and Systems, vol. 4, no. 6, pp. 426-436, 2010.
  • An array of memristors fabricated in collaboration with the Functional Materials and Microsystems research group at RMIT. Kavehei, O.; Al-Sarawi, S.F.; Cho, K.R.; Iannella, N.; Kim, S.; Eshraghian, K.; and Abbott, D.; "Memristor-based synaptic networks and logical operations using in-situ computing," International Conference Series on Intelligent Sensors, Sensor Networks and Information Processing, ISSNIP, accepted on September 26, 2011. Kavehei, O.; Cho K.R.; Lee S.J. Kim S.J.; Al-Sarawi S.; Abbott D.; Eshraghian K.; "Fabrication and Modeling of Ag/TiO$_{2}$/ITO Memristor," 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS, Seoul, South Korea, August, 2011.

Research Focus:
Architectures for Artificial Intelligence

Our aim is to create new machines, inspired by nature and better suited to problems from the field of Artificial Intelligence than the ubiquitous von Neumann architecture used in today's microprocessors.

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Research Focus:
Integrated RF Systems

The aim is to design single-chip RF systems integrating everything from the analog RF front-end to the digital baseband processing. This research focus brings together many of CHiPTec's areas of expertise including RF and analog design, DSP and MIMO radar.

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