ELEC ENG 3109 - Digital Microelectronics

North Terrace Campus - Semester 1 - 2019

Introduction to fabrication processes; Design rules (revisited); Transistor models (revisited from second year electronics); Layout issues; ASIC design flow; VLSI design methodology and leaf cell design; Performance estimation of CMOS complex gates and interconnected modules using logical effort; Interconnect types and issues, clock distribution, design margin, reliability and scaling; Static and dynamic CMOS logic families and adders design; Memories-static and dynamic RAMS, Pseudo-NMOS and dynamic PLA; Low power design and system level consideration.

  • General Course Information
    Course Details
    Course Code ELEC ENG 3109
    Course Digital Microelectronics
    Coordinating Unit School of Electrical & Electronic Engineering
    Term Semester 1
    Level Undergraduate
    Location/s North Terrace Campus
    Units 3
    Contact Up to 4 hours per week
    Available for Study Abroad and Exchange
    Prerequisites ELEC ENG 2101
    Incompatible ELEC ENG 4053
    Assumed Knowledge ELEC ENG 2100
    Course Description Introduction to fabrication processes; Design rules (revisited); Transistor models (revisited from second year electronics); Layout issues; ASIC design flow; VLSI design methodology and leaf cell design; Performance estimation of CMOS complex gates and interconnected modules using logical effort; Interconnect types and issues, clock distribution, design margin, reliability and scaling; Static and dynamic CMOS logic families and adders design; Memories-static and dynamic RAMS, Pseudo-NMOS and dynamic PLA; Low power design and system level consideration.
    Course Staff

    Course Coordinator: Dr Said Al-Sarawi

    Course Timetable

    The full timetable of all activities for this course can be accessed from Course Planner.

  • Learning Outcomes
    Course Learning Outcomes
    On successful completion of this course students will be able to:

     
    1 ExplainCMOS technology fabrication and device characteristics and parasitic effects.
    2 Design digital logic gates and standard cells at transistor schematic and
    corresponding layouts level in CMOS technology using pseudo-nMOS, pass
    transistor, footed and footless domino logic families.
    3 Explain and evaluate the effect of the parasitic and loading on CMOS circuit
    operation and performance in terms of size, area and noise margin and ways to
    minimise delay.
    4 Model the effect of interconnect upon a design and to apply strategies to mitigate
    problems arising from interconnect loading.

    5 Explain the function of CMOS memory circuits and design basic CMOS ROM and PLA
    circuits.
    6 Explain factors that influence circuit reliability and be able to apply reasonable
    design margins.
    7 Explain the effect of scaling on circuit behaviour and appreciate technology trends
    with respect to scaling.
    8 Explain system level considerations such as floor planning, power dissipation, clock
    skew and micro-architecture to system performance.
    9 Use a set of software tools to specify, synthesise, layout and simulate
    microelectronic circuits.
    10 Work as part of a team to design a system module.

     
    The above course learning outcomes are aligned with the Engineers Australia Stage 1 Competency Standard for the Professional Engineer.
    The course is designed to develop the following Elements of Competency: 1.1   1.2   1.3  1.4  1.5  1.6   2.1   2.2   2.3  2.4    3.1   3.2   3.3   3.4   3.5   3.6   

    University Graduate Attributes

    This course will provide students with an opportunity to develop the Graduate Attribute(s) specified below:

    University Graduate Attribute Course Learning Outcome(s)
    Deep discipline knowledge
    • informed and infused by cutting edge research, scaffolded throughout their program of studies
    • acquired from personal interaction with research active educators, from year 1
    • accredited or validated against national or international standards (for relevant programs)
    1, 4, 6, 7, 8
    Critical thinking and problem solving
    • steeped in research methods and rigor
    • based on empirical evidence and the scientific approach to knowledge development
    • demonstrated through appropriate and relevant assessment
    2, 3, 5, 8
    Teamwork and communication skills
    • developed from, with, and via the SGDE
    • honed through assessment and practice throughout the program of studies
    • encouraged and valued in all aspects of learning
    9, 10
    Career and leadership readiness
    • technology savvy
    • professional and, where relevant, fully accredited
    • forward thinking and well informed
    • tested and validated by work based experiences
    2, 6, 8, 9
    Self-awareness and emotional intelligence
    • a capacity for self-reflection and a willingness to engage in self-appraisal
    • open to objective and constructive feedback from supervisors and peers
    • able to negotiate difficult social situations, defuse conflict and engage positively in purposeful debate
    10
  • Learning & Teaching Activities
    Learning & Teaching Modes

    No information currently available.

    Workload

    No information currently available.

    Learning Activities Summary

    No information currently available.

  • Assessment

    The University's policy on Assessment for Coursework Programs is based on the following four principles:

    1. Assessment must encourage and reinforce learning.
    2. Assessment must enable robust and fair judgements about student performance.
    3. Assessment practices must be fair and equitable to students and give them the opportunity to demonstrate what they have learned.
    4. Assessment must maintain academic standards.

    Assessment Summary
    Assessment Task Weighting (%) Individual/ Group Formative/ Summative
    Due (week)*
    Hurdle criteria Learning outcomes
    Computer Lab 1 2 Individual
    Diagnostic
    Weeks 1-3  2. 3. 9.
    Computer Lab 2 3 Individual
    Diagnostic
    Weeks 4-6  2. 3. 9.
    Computer Lab3 5 Individual
    Diagnostic
    Weeks 7-8 .2. 3. 4. 9.
    Computer Lab 4 15 Group
    Summative
    Weeks 9-12 2. 3. 4. 5. 8. 9 .10
    Test 10 Individual
    Summative
    Week 10 1. 2. 3. 4. 5. 6. 7. 8.
    Exam 65 Individual
    Summative
    Exam period Min 40% 1. 2. 3. 4. 5. 6. 7. 8.
    * The specific due date for each assessment task will be available on MyUni.
     
    This assessment breakdown is registered as an exemption to the University's Assessment for Coursework Programs Policy. The exemption is related to the Procedures clause(s): 1. b. 3.   
     
    This course has a hurdle requirement. Meeting the specified hurdle criteria is a requirement for passing the course.
    Assessment Detail

    No information currently available.

    Submission

    No information currently available.

    Course Grading

    Grades for your performance in this course will be awarded in accordance with the following scheme:

    M10 (Coursework Mark Scheme)
    Grade Mark Description
    FNS   Fail No Submission
    F 1-49 Fail
    P 50-64 Pass
    C 65-74 Credit
    D 75-84 Distinction
    HD 85-100 High Distinction
    CN   Continuing
    NFE   No Formal Examination
    RP   Result Pending

    Further details of the grades/results can be obtained from Examinations.

    Grade Descriptors are available which provide a general guide to the standard of work that is expected at each grade level. More information at Assessment for Coursework Programs.

    Final results for this course will be made available through Access Adelaide.

  • Student Feedback

    The University places a high priority on approaches to learning and teaching that enhance the student experience. Feedback is sought from students in a variety of ways including on-going engagement with staff, the use of online discussion boards and the use of Student Experience of Learning and Teaching (SELT) surveys as well as GOS surveys and Program reviews.

    SELTs are an important source of information to inform individual teaching practice, decisions about teaching duties, and course and program curriculum design. They enable the University to assess how effectively its learning environments and teaching practices facilitate student engagement and learning outcomes. Under the current SELT Policy (http://www.adelaide.edu.au/policies/101/) course SELTs are mandated and must be conducted at the conclusion of each term/semester/trimester for every course offering. Feedback on issues raised through course SELT surveys is made available to enrolled students through various resources (e.g. MyUni). In addition aggregated course SELT data is available.

  • Student Support
  • Policies & Guidelines
  • Fraud Awareness

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