Dr Braden Phillips

Dr Braden Phillips
 Position Senior Lecturer
 Org Unit School of Electrical and Electronic Engineering
 Email braden.phillips@adelaide.edu.au
 Telephone +61 8 8313 5114
 Location Floor/Room 3 38 ,  Ingkarni Wardli ,   North Terrace
  • Biography/ Background

    Senior Lecturer
    Ph.D., B.E. (Hons), B.Sc., MIEEE

    ResearcherID: A-8373-2008 

    Braden Phillips is a senior lecturer in the School of Electrical and Electronic Engineering at the University of Adelaide and is director of CHiPTec, the The Centre for High Performance Integrated Technologies and Systems. 

    Braden’s research focus is the design of new computing architectures for artificial intelligence, and in particular the Street Engine processor for cognitive computing. This work draws upon his research interest and experience in digital arithmetic, digital microelectronics, computer architecture, information security, and real-time and embedded systems.

    Prior to the completion of his PhD thesis, ’An Optimised Implementation of Public Key Cryptography for Smart Card Processors’, Braden worked as a process control engineer and was a founding partner in Current Dynamics, an electronic hardware design venture. He was a lecturer at Cardiff University in South Wales for 2 years before returning to the University of Adelaide in 2002.

  • Research Interests

    Research Projects:

    • The Street Project to design a new computer architecture for artificial intelligence and cognitive computing.
    • Dynamically Reconfigurable Networks on Chip

    Related Research Interests:

    • Computer Architecture Processor architectures for artificial intelligence and cognitive computing, data value speculation, application specific architectures
    • Digital Arithmetic Hardware for integer and floating point operations, number systems, estimating arithmetic
    • Information Security Implementing cryptography, circumventing side-channel attacks, semiconductor remanence
    • Digital Microelectronics Low-power and high-performance circuits, subthreshold logic, fault tolerant circuits


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Entry last updated: Thursday, 16 Aug 2018

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