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Dr Cruz Izu

Telephone +61 8 8313 5762
Position Lecturer
Email cruz@cs.adelaide.edu.au
Fax +61 8 8313 4366
Building Ingkarni Wardli
Floor/Room 4 20
Campus North Terrace
Org Unit School of Computer Science

To link to this page, please use the following URL:
http://www.adelaide.edu.au/directory/cruz.izu

Biography/ Background

Cruz hold a B Sc Hons (Computer Science) and a PhD (Computer Architecture) from the University of the Basque Country, and a Graduate Certificate on Online learning for UoA.

Cruz has a long-term research collaboration with the ATC group at the University of Cantabria, working on the area of Interconnection networks; she has also collaborate in 2012-2016  with the GAZ group at the University of Zaragoza. 

Cruz  has a large experience teaching at UoA, from small groups of 15 students to large classes of 300. She believes students learn most by doing, so her classes mix lectures with examples, exercises and quizzes. Her role as a teacher is mainly to observe students efforts, provide support and feedback so they reach their goals and give guidance when required. 

Since 2011, Cruz has led the outreach program CS4HS which helps middle and high school teachers introduce Computer Science and computational thinking into their school curriculum. She has recently participated in the write up for the new SACE course Digital Techonologies, which will be implemented in 2018 (Stage1) and 2019 (Stage2). 

Cruz has becomed research active in the area of Computer Science education in the last 4 years,  exploring both outreach topics and teaching programming skills to first year university students.  

Teaching Interests

Cruz has regularly taught and develop teaching materials for Computer Systems, Operating Systems and Computer Architecture.  

Together with Dr Alexander, in 2009 she redeveloped the PG  course "Specialised Programming", and in 2014 adapted that scheme into the undergraduate stream as the new course  "Problem Solving and Software Development". 

Other courses regularly taught by Dr Izu include "MCI project"  and "Introduction to Programming for Engineers". 

 

Research Interests

Cruz is research active into two areas

  1. Parallel Architecures and Interconnection Networks: covering Networks on chip, routing, network evaluation, network design. 
  2. Computer Science Education: probelm solving, teaching novice programmers, and computational thinking in schools. 

Publications

Journal Papers

Ortín-Obón, M., Suárez-Gracia, D., Villarroya-Gaudó, M., Izu, C., & Viñals, V. (2016).Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous  CMPs. Journal of Parallel and Distributed Computing, 95, 57-68. doi:10.1016/j.jpdc.2016.04.002

Ortín-Obón, M., Suárez-Gracia, D., Villarroya-Gaudó, M., Izu, C., & Viñals-Yúfera, V. (2016). Analysis of network-on-chip topologies for cost-efficient chip multiprocessors. Microprocessors and Microsystems, 42, 24-36. doi:10.1016/j.micpro.2016.01.005

Miguel-Alonso, J., Izu, C., & Gregorio, J. (2008). Improving the performance of large interconnection networks using congestion-control mechanisms. Performance Evaluation, 65(3-4), 203-211. doi:10.1016/j.peva.2007.05.001

Puente, V., Gregorio, J., Vallejo, F., Beivide, R., & Izu, C. (2006). High-performance adaptive routing for networks with arbitrary topology. Journal of Systems Architecture, 52(6), 345-358. doi:10.1016/j.sysarc.2005.09.003

Martinez, C., Vallejo, E., Beivide, R., Izu, C., & Moreto, M. (2006). Dense Gaussian networks: Suitable topologies for on-chip multiprocessors. International Journal of Parallel Programming, 34(3), 193-211. doi:10.1007/s10766-006-0014-1

Izu, C., Miguel-Alonso, J., & Gregorio, J. (2005). Evaluation of interconnection network performance under heavy non-uniform loads. Lecture Notes in Computer Science/Lecture Notes in Artificial Intelligence, 3719, 396-405. doi:10.1007/11564621_46

Puente, V., Gregorio, J., Beivide, R., & Izu, C. (2003). On the design of a high-performance adaptive router for CC-NUMA multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 14(5), 487-501. doi:10.1109/TPDS.2003.1199066

Puente, V., Izu, C., Beivide, R., Gregorio, J., Vallejo, F., & Prellezo, J. (2001). The adaptive bubble router. Journal of Parallel and Distributed Computing, 61(9), 1180-1208. doi:10.1006/jpdc.2001.1746

Education conference papers

Izu, C., Weerasinghe, A., & Pope, C. (2016). A Study of Code Design Skills in Novice Programmers using the SOLO taxonomy. In Proceedings of the 2016 ACM Conference on International Computing Education Research (pp. 251-259). New York, USA: ACM. doi:10.1145/2960310.2960324

Barendsen, E., Mannila, L., Demo, B., Grgurina, N., Izu, C., Mirolo, C., . . . StupurienÄ—, G. (2015). Concepts in K-9 Computer Science Education. In ITICSE-WGR '15 Proceedings of the 2015 ITiCSE on Working Group Reports (pp. 85-116). New York, NY, US: ACM. doi:10.1145/2858796.2858800

Izu, C., & Weerasinghe, A. (2014). Flowcharts: A tool for computational thinking. In Conference Proceedings of the 26th Australian Computers in Education Conference 2014 (pp. 305-313). Adelaide.

Alexander, B., & Izu, C. (2010). Engaging weak programmers in problem solving. In Proceedings of IEEE EDUCON Education Engineering 2010 - The Future of Global Learning Engineering Education (pp. 997-1005). USA: IEEE. doi:10.1109/EDUCON.2010.5492468

Computer Architecture Conference Papers 

Benito, M., Vallejo, E., Beivide, R., & Izu, C. (2017). Extending Commodity OpenFlow Switches for Large-Scale HPC Deployments. In 2017 IEEE 3rd International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB),. Austin, TX, USA: IEEE. doi:10.1109/HiPINEB.2017.12

Ortín, M., Suárez, D., Villarroya, M., Izu, C., & Viñals, V. (2014). Dynamic construction of circuits for reactive traffic in homogeneous CMPs. In Proceedings: Design, Automation & Test in Europe (pp. 1-4). Dresden, Germany: Institute of Electrical and Electronics Engineers. doi:10.7873/DATE2014.254

Ortin Obon, M., Suarez Gracia, D., Villarroya Gaudo, M., Izu, C., & Vinals Yufera, V. (2013). Reserva de circuitos para tráfico reactivo en CMPs homogéneos. In G. Botella, & A. Del Barrio Garcia (Eds.), Actas de las XXIV Jornadas de Paralelismo Vol. 1 (pp. 36-42). Madrid: Universidad Complutense de Madrid.

Ortin, M., Ferreron, A., Albericio, J., Suarez, D., Villarroya-Gaudo, M., Izu, C., & Vinals, V. (2013). Characterization and cost-efficient selection of NoC topologies for general purpose CMPs. In Proceedings of the 7th International Workshop on Interconnection Network Architecture On-Chip, Multi-Chip, INA-OCMC 2013 (pp. 1-4). online: ACM. doi:10.1145/2482759.2482765

Izu, C., & Vallejo, E. (2012). Throughput fairness in indirect interconnection networks. In Proceedings of the IEEE 2012 13th International Conference on Parallell and Distributed Computing, Applications and Technologies (pp. 233-238). CD: IEEE. doi:10.1109/PDCAT.2012.129

Izu, C. (2011). On the use of multiplanes on a 2D mesh network-on-chip. In Proceedings of ICA3PP 2011 Vol. 7017 LNCS (pp. 276-286). Germany: Springer-Verlag. doi:10.1007/978-3-642-24669-2_27

Izu, C. (2009). A throughput fairness injection protocol for mesh and torus networks. In Proceedings of HiPC2009 (pp. 1-10). India: ACM. doi:10.1109/HIPC.2009.5433198

Ridruejo, F., Navaridas, J., Miguel-Alonso, J., & Izu, M. (2007). Realistic evaluation of interconnection network performance at high loads. In D. S. Munro (Ed.), Proceedings of PDCAT 2007 (pp. 97-104). USA: IEEE. doi:10.1109/PDCAT.2007.73

Izu, C. (2006). Throughput fairness in k-ary n-cube networks. In V. Estivill-Castro, & G. Dobbie (Eds.), Proceedings of ACSC 2006 Vol. 48 (pp. 137-145). Australia: Australian Computer Society.Izu, M., Miguel-Alonso, J., & Gregorio, J. (2006). Effects of injection pressure on network throughput. In J. D. Cantarella (Ed.), Proceedings of the 14th Euromicro International Conference on Parallel, Distributed, and Network-based Processing Vol. 2006 (pp. 91-98). USA: IEEE. doi:10.1109/PDP.2006.32

Luque, E., Izu, C., Lysne, O., & Legatheaux, J. (2005). Topic 13 routing and communication in interconnection networks. In Lecture Notes in Computer Science Vol. 3648 (pp. 973).

Izu, C., & Beivide, R. (2004). Understanding buffer management for cut-through 1D rings. In M. Danelutto, D. Laforenza, & M. Vanneschi (Eds.), Proceedings of the 10th Euro-Par 2004 Conference on Parallel Processing Vol. 3149 (pp. 908-915). Berlin, Germany: Springer. doi:10.1007/b99409

Izu, C., Beivide, R., & Gregorio, J. (2004). The case of chaotic routing revisited. In B. Black, & M. Lipasti (Eds.), Proceedings of the 3rd Annual Workshop on Duplicating, Deconstructing, and Debunking 2004 (pp. www 32-www 40). http://www.ece.wisc.edu/~wddd/2004/04_izu.pdf: WDDD. Retrieved from http://www.ece.wisc.edu/~wddd/2004/WDDD2004_proceedings.pdf

Martinez, C., Beivide, R., Gutierrez, J., & Izu, M. (2003). Distance-hereditary embeddings of circulant graphs. In P. K. Srimani (Ed.), Proceedings of ITCC 2003 (pp. 320-324). USA: IEEE. doi:10.1109/ITCC.2003.1197548

Beivide, R., Martinez, C., Izu, C., Gutierrez, J., Gregorio, J., & Miguel-Alonso, J. (2003). Chordal topologies for interconnection networks. In A. Veidenbaum, K. Joe, H. Amano, & H. Aiso (Eds.), 5th International Symposium, ISHPC 2003 Toyko-Odabia, Japan, October 2003 Proceedings Vol. 2858 (pp. 385-392). Berlin, Germany: Springer. doi:10.1007/978-3-540-39707-6_33 

Beivide, R., Jesshope, C., Robles, A., & Izu, C. (2001). Topic 12, routing and communication in interconnection networks. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) Vol. 2150 (pp. 611-612).

Puente, V., Izu, M., Gregorio, J., Beivide, R., Prellezo, J., & Vallejo, F. (2000). Improving parallel system performance by changing the arrangement of the network links. In A. Veidenbaum (Ed.), Proceedings of the 2000 International Conference on Supercomputing (pp. 44-53). New Mexico, USA: ICS. doi:10.1145/335231.335236

Puente, V., Prellezo, J. M., Izu, C., Gregorio, J. A., & Beivide, R. (2000). A case study of trace-driven simulation for analyzing interconnection networks: cc-NUMAs with ILP processors. In Proceedings - 8th Euromicro Workshop on Parallel and Distributed Processing, EURO-PDP 2000 (pp. 174-180). doi:10.1109/EMPDP.2000.823409

 

Entry last updated: Thursday, 30 Mar 2017

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