ELEC ENG 7051 - Microelectronic Systems
North Terrace Campus - Semester 1 - 2019
General Course Information
Course Code ELEC ENG 7051 Course Microelectronic Systems Coordinating Unit School of Electrical & Electronic Engineering Term Semester 1 Level Postgraduate Coursework Location/s North Terrace Campus Units 3 Contact Up to 6 hours per week Available for Study Abroad and Exchange Y Incompatible ELEC ENG 4053 Assumed Knowledge Linear circuit analysis techniques, operation & characteristic of field effect transistor Course Description Introduction to fabrication processes, design rules (revisited); Transistor models (revisited from third year electronics); Layout issues; ASIC design flow; VLSI design methodology and leaf cell design; Performance estimation of CMOS complex gates and interconnected modules using logical effort; Interconnect issues; Clock distribution; Design margin, reliability and scaling; Static and dynamic CMOS logic families and adders design; Memories - static and dynamic RAMS; Pseudon-NMOS and dynamic PLA; Low power design and system level consideration.
Course Coordinator: Dr Said Al-SarawiCourse Coordinator and Lecturer: Dr Said Al-Sarawi
Office: Ingkarni Wardli 3.39
The full timetable of all activities for this course can be accessed from Course Planner.
Course Learning OutcomesOn successful completion of this course students will be able to:
1 Explain CMOS technology fabrication and device characteristics and parasitic effects 2 Design digital logic gates and standard cells at transistor schematic and corresponding layouts level in CMOS technology using pseudo-nMOS, pass transistor, footed and footless domino logic families. 3 Explain and evaluate the effect of the parasitic and loading on CMOS circuit operation and performance in terms of size, area and noise margin and ways to minimise delay. 4 Model the effect of interconnect upon a design and to apply strategies to mitigate problems arising from interconnect loading. 5 Explain the function of CMOS memory circuits and design basic CMOS ROM and PLA circuits. 6 Explain factors that influence circuit reliability and be able to apply reasonable design margins. 7 Explain the effect of scaling on circuit behaviour and appreciate technology trends with respect to scaling. 8 Explain system level considerations such as floor planning, power dissipation, clock skew and micro-architecture to system performance. 9 Use a set of software tools to specify, synthesise, layout and simulate microelectronic circuits. 10 Demonstrate team work to design a system module
The above course learning outcomes are aligned with the Engineers Australia Stage 1 Competency Standard for the Professional Engineer.
The course is designed to develop the following Elements of Competency: 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 3.1 3.2 3.3 3.4 3.5 3.6
University Graduate Attributes
This course will provide students with an opportunity to develop the Graduate Attribute(s) specified below:
University Graduate Attribute Course Learning Outcome(s) Deep discipline knowledge
- informed and infused by cutting edge research, scaffolded throughout their program of studies
- acquired from personal interaction with research active educators, from year 1
- accredited or validated against national or international standards (for relevant programs)
1,4,6,7,8 Critical thinking and problem solving
- steeped in research methods and rigor
- based on empirical evidence and the scientific approach to knowledge development
- demonstrated through appropriate and relevant assessment
2,3,5,8 Teamwork and communication skills
- developed from, with, and via the SGDE
- honed through assessment and practice throughout the program of studies
- encouraged and valued in all aspects of learning
9-10 Career and leadership readiness
- technology savvy
- professional and, where relevant, fully accredited
- forward thinking and well informed
- tested and validated by work based experiences
2,6,9,10 Self-awareness and emotional intelligence
- a capacity for self-reflection and a willingness to engage in self-appraisal
- open to objective and constructive feedback from supervisors and peers
- able to negotiate difficult social situations, defuse conflict and engage positively in purposeful debate
Neil H. E. Weste & David Harris, “CMOS VLSI design: a circuits and systems perspective,” Addison Wesley, 3rd edition, 2004.
Rabaey, Chandrakasan & Nikolil, “Digital Integrated Circuits,” Prentice Hall, 2nd edition, 2003.
A set of course notes, practice problems and other supporting materials will also be available for downloading from the course web site.
Online LearningExtensive use will be made of the MyUni web site for this course,
Course notes, tutorial problems and solutions, laboratory exercises and practice problems will all be available for downloading from the web site. Where the lecture theatre facilities permit, audio or video recordings of lectures will also be available for downloading.
Learning & Teaching Activities
Learning & Teaching ModesThis course relies on lectures as the primary delivery mechanism for the material. Tutorials supplement the lectures by providing exercises and example problems to enhance the understanding obtained through lectures. Practicals are used to provide hands-on experience for students to reinforce the theoretical concepts encountered in lectures. Continuous assessment activities provide the formative assessment opportunities for students to gauge their progress and understanding.
The information below is provided as a guide to assist students in engaging appropriately with the course requirements.The information below is provided as a guide to assist students in engaging appropriately with the course requirements.
Activity Contact Hours Workload Hours Lecture 24 Lectures 24 48 Tutorials 5 Tutorials 5 10 Practicals Computer Lab 1 3 6 Computer Lab 2 3 8 Computer Lab 3 3 8 Computer Lab 4 6 24 Test Theory part of the course 1 6 Exam All Theory Part 3 30 48 140
Learning Activities Summary
Lectures Activity Session No. Week No of Lectures Introduction to the course and presentation of prac structure 1&2 1 2 Introduction to fabrication processes, design rules (revisted). Transistor models (revisited from third year electronics) and layout issues and ASIC design flow 2&3 2 2 VLSI design methodology and leaf cell design 4&5 3 2 Performance estimation of CMOS complex gates and interconnected modules using logical effort 6-13 4-7 8 Interconnect issues, clock distribution, design margin, reliability and scaling 14-17 8,9 4 Static and dynamic CMOS logic families and adders design 18,19,20 10,11 2 Memory structures and operation 21,22 11,12 2 Low power design and system level consideration 23-24 12 2 Tutorials Activity Sessions Week Topic Demonstrating the design of CMOS gates and transistor sizing 1 4 Tutorial 1 CMOS circuits layout and delay estimation 2 6 Tutorial 2 CMOS circuits delay estimation using logical effort 3 8 Tutorial 3 Delay path estimation using logical effort 4 10 Tutorial 4 Delay and crosstalk in interconnects 5 12 Tutorial 5
Note that practical classes begin in week 1 of the semester and run in odd weeks. Students must attend their allocated practical class, when further instructions on the operation of the laboratory session will be provided. Students should be aware of the Occupational Health and Safety issues associated with working in a laboratory environment.
The University's policy on Assessment for Coursework Programs is based on the following four principles:
- Assessment must encourage and reinforce learning.
- Assessment must enable robust and fair judgements about student performance.
- Assessment practices must be fair and equitable to students and give them the opportunity to demonstrate what they have learned.
- Assessment must maintain academic standards.
Assessment Task Weighting (%) Individual/ Group Formative/ Summative Due (week)* Hurdle criteria Learning outcomes Computer Lab 1 2 Individual Diagnostic Weeks 1-3 2. 3. 9. Computer Lab 2 3 Individual Diagnostic Weeks 4-6 2. 3. 9. Computer Lab3 5 Individual Diagnostic Weeks 7-8 2. 3. 4. 9. Computer Lab 4 20 Group Summative Weeks 9-12 2. 3. 4. 5. 8. 9. 10. Test 10 Individual Summative Week 10 1. 2. 3. 4. 5. 6. 7. 8. Exam 60 Individual Summative Week 14 Min 40% 1. 2. 3. 4. 5. 6. 7. 8. Total 100
This assessment breakdown complies with the University's Assessment for Coursework Programs Policy.
This course has a hurdle requirement. Meeting the specified hurdle criteria is a requirement for passing the course.
Assessment DetailThe examination is a hurdle requirement. It is necessary to achieve at least 40% in the exam. If this is not achieved, the total course mark will be limited to a maximum of 49.
A hurdle requirement is defined by the University's Assessment for Coursework Programs policy as "...an assessment task mandating a minimum level of performance as a condition of passing the course.If a student fails to meet a hurdle requirement (normally no less than 40%),and is assigned a total mark for the course in the range of 45-49, then the student is entitled to an offer of additional assessment of some type. The type of assessment is to be decided by the School Assessment Review Committee when determining final results. The student’s final total mark will be entered at no more than 49% and the offer of an additional assessment will be specified eg. US01. Once the additional assessment has been completed, this mark will be included in the calculation of the total mark for the course and the better of the two results will apply. Note however that the maximum final result for a course in which a student has sat an additional assessment will be a “50 Pass”.
If a student is unable to meet a hurdle requirement related to an assessment piece (may be throughout semester or at semester’s end) due to medical or compassionate circumstances beyond their control, then the student is entitled to an offer of replacement assessment of some type. An interim result of RP will be entered for the student, and the student will be notified of the offer of a replacement assessment. Once the replacement assessment has been completed, the result of that assessment will be included in the calculation of the total mark for the course.An assessment of work done during the lab will be conducted at the end of each lab session.
SubmissionSubmission will be through MyUni and information on the process will be provided for each assignment in due course.
Grades for your performance in this course will be awarded in accordance with the following scheme:
M10 (Coursework Mark Scheme) Grade Mark Description FNS Fail No Submission F 1-49 Fail P 50-64 Pass C 65-74 Credit D 75-84 Distinction HD 85-100 High Distinction CN Continuing NFE No Formal Examination RP Result Pending
Further details of the grades/results can be obtained from Examinations.
Grade Descriptors are available which provide a general guide to the standard of work that is expected at each grade level. More information at Assessment for Coursework Programs.
Final results for this course will be made available through Access Adelaide.
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SELTs are an important source of information to inform individual teaching practice, decisions about teaching duties, and course and program curriculum design. They enable the University to assess how effectively its learning environments and teaching practices facilitate student engagement and learning outcomes. Under the current SELT Policy (http://www.adelaide.edu.au/policies/101/) course SELTs are mandated and must be conducted at the conclusion of each term/semester/trimester for every course offering. Feedback on issues raised through course SELT surveys is made available to enrolled students through various resources (e.g. MyUni). In addition aggregated course SELT data is available.
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