ELEC ENG 2100 - Digital Systems
North Terrace Campus - Semester 1 - 2022
General Course Information
Course Code ELEC ENG 2100 Course Digital Systems Coordinating Unit School of Electrical & Electronic Engineering Term Semester 1 Level Undergraduate Location/s North Terrace Campus Units 3 Contact Up to 2 hours per week Available for Study Abroad and Exchange Y Prerequisites ELEC ENG 1102 Incompatible ELEC ENG 3028 Course Description This course develops engineering capabilities pertaining to the design of digital electronic systems. Designs for contemporary implementation technologies are expressed using circuit schematics and SystemVerilog, at levels of abstraction from CMOS transistor circuits up to processor microarchitecture. System architecture, microarchitecture and interfacing concepts are developed through an extended case study of a commercial microprocessor. The course operates as a flipped classroom with students attending weekly 2-hour tutorials. Preparatory lectures, reading and exercise questions are completed before tutorials. Tutorial problems are more open-ended and typically require discussion in small groups, practical design, simulation and implementation using computers and reconfigurable logic circuits. Students also undertake a group research exercise on a question related to the future of digital electronics technology.
Course Coordinator: Dr Alok Kushwaha
The full timetable of all activities for this course can be accessed from Course Planner.The course is delivered in a flipped format with pre-recorded slide presentations available online for preparation ahead of tutorials. Each student attends a 2-hour tutorial every week. These tutorials involve individual and small group activities, class discussions, and problem solving activities including computer-based design and simulation.
A weekly 1-hour workshop session is schedule available for optional drop-in assistance. In weeks 4, 7 and 10 this session will be used for the mid-semester tests.
Course Learning OutcomesOn successful completion of this course students will be able to:
1 Design, build and test digital logic for systems of moderate complexity using common digital components, schematic diagrams, and hardware description language 2 Use and explain engineering practices to manage the complexity of digital systems 3 Use appropriate implementation technologies for digital systems 4 Design CMOS logic gates at the transistor schematic level 5 Explain, extend and compare alternative microarchitectures for a RISC microprocessor 6 Work effectively and ethically in teams to undertake the design of digital systems 7 Prepare and present a written answer to a research question relating to future electronic technologies
The above course learning outcomes are aligned with the Engineers Australia Stage 1 Competency Standard for the Professional Engineer.
The course is designed to develop the following Elements of Competency: 1.1 1.2 1.3 1.4 1.5 2.1 2.2 2.3 2.4 3.2 3.4 3.5 3.6
University Graduate Attributes
This course will provide students with an opportunity to develop the Graduate Attribute(s) specified below:
University Graduate Attribute Course Learning Outcome(s)
Attribute 1: Deep discipline knowledge and intellectual breadth
Graduates have comprehensive knowledge and understanding of their subject area, the ability to engage with different traditions of thought, and the ability to apply their knowledge in practice including in multi-disciplinary or multi-professional contexts.
Attribute 2: Creative and critical thinking, and problem solving
Graduates are effective problems-solvers, able to apply critical, creative and evidence-based thinking to conceive innovative responses to future challenges.
Attribute 3: Teamwork and communication skills
Graduates convey ideas and information effectively to a range of audiences for a variety of purposes and contribute in a positive and collaborative manner to achieving common goals.
Attribute 4: Professionalism and leadership readiness
Graduates engage in professional behaviour and have the potential to be entrepreneurial and take leadership roles in their chosen occupations or careers and communities.
Attribute 5: Intercultural and ethical competency
Graduates are responsible and effective global citizens whose personal values and practices are consistent with their roles as responsible members of society.
Attribute 8: Self-awareness and emotional intelligence
Graduates are self-aware and reflective; they are flexible and resilient and have the capacity to accept and give constructive feedback; they act with integrity and take responsibility for their actions.
Required ResourcesTextbook: David Harris and Sarah Harris, Digital Design and Computer Architecture, Elsevier, Second Edition (2013). The full text of this book is available electronically from the University of Adelaide Library.
A set of slides, recorded slide show presentations, practice problems, worked solutions, and other supporting materials will be available for downloading from the course web site. FPGA development board will be available for loan to students. These will be used in tutorials and may also be used in a student’s own time, in the computer aided teaching suites for example.
Online LearningThis course uses the MyUni web site. All announcements are posted on MyUni. Recorded slide show presentations, practice and tutorial questions, and other resources are available on MyUni. The gradebook is used to communicate marks. The research assignment is submitted using MyUni. A discussion board is available for course-related discussion.
Learning & Teaching Activities
Learning & Teaching ModesTutorials: the course uses a flipped classroom with an emphasis on weekly 2-hour face-to-face tutorials. Students prepare for tutorials by reading sections of the textbook, watching pre-recorded lectures, and attempting preparation exercises. During tutorials, teaching staff spend time with each student individually to help explain difficult concepts. Tutorial time is also spent working as individuals on exercise problems and in small groups on design problems.
Recorded Slide Shows: wherever possible the slide shows follow the structure, terminology and notation of the course textbook. Slides and recoded presentations are available prior to tutorials and, where material outside of the scope of the textbook is presented, detailed notes are provided. Students are expected to read sections of the textbook, watch the side presentations and attempt some exercise problems in preparation for tutorials.
The information below is provided as a guide to assist students in engaging appropriately with the course requirements.The information below is provided as a guide to help students engage appropriately with the course requirements.
Activity Contact Hours Workload Hours Pre-tutorial Reading 36 Recorded Slide Presentaions 36 Tests 3 6 Tutorials 24 36 Research Assignment 1 4 Practice Questions and Revision 32 Total 28 150
Learning Activities SummaryTOPIC 1: Building Digital Systems
Managing complexity: design goals, abstraction, hierarchy, modularity and regularity
The digital abstraction: digital signals, logic gates, truth tables and Boolean equations, number systems
Implementation technologies: discrete logic chips, microprocessors, programmable logic controllers, PLCs, ASICsI
Introduction to SystemVerilog: signals and operators, continuous assignments, structural models, testbenches
TOPIC 2: Combinational Logic Design
Review: Boolean equations, Boolean algebra, simplification, Karnaugh maps
Logic synthesis: manual techniques, combinational logic in SystemVerilog
High impedance & illegal logic states
Combinational blocks: multiplexers, decoders, tristates
Timing: propagation and contamination delay, glitches
TOPIC 3: Sequential Logic Design
Synchronous elements: latches, flip-flops, SystemVerilog
Synchronous circuits: asynchronous logic, synchronous architectures
Synthesis of synchronous logic: systematic synthesis, ad-hoc synthesis, state encoding, Mealy and Moore machines, factoring, analysing FSMs, SystemVerilog
Advanced SystemVerilog: parameterised models, test benches
Parallelism: latency & throughput, pipelines
Timing: constraints, clock skew, synchronisation
TOPIC 4: CMOS Logic
CMOS logic gates: MOSFETs, static CMOS, transmission gates, pseudo-nMOS
Delay: transistor sizing, RC model, rise and fall time, linear delay model, noise margin
Power: dynamic power, static power, low power design
TOPIC 5: Digital Subsystems and Interfaces
Arithmetic subsystems: adders, subtractors and comparators, shifts and rotates, ALUs, fixed point representation
Sequential subsystems: counters, shift registers, scan chains
Memory subsystems: organisation, memory types, memory applications
Logic array subsystems: PLAs, FPGAs
Parallel interfaces: nomenclature, bidirectional signals, memory mapping, memory organisation, memory addressing
Serial interfaces: asynchronous serial, synchronous serial
Building blocks: tristates, multiplexers, adders, latches, flip-flops, memory cells
TOPIC 6: Processor Microarchitecture
Review: instruction set architecture, machine language
Single cycle processor: datapath, control, performance
Multicycle processor: datapath, control, performance
Pipelined processor: datapath, control, hazards, performance
The University's policy on Assessment for Coursework Programs is based on the following four principles:
- Assessment must encourage and reinforce learning.
- Assessment must enable robust and fair judgements about student performance.
- Assessment practices must be fair and equitable to students and give them the opportunity to demonstrate what they have learned.
- Assessment must maintain academic standards.
Assessment Task Weighting (%) Individual/ Group Formative/ Summative Due (week)* Hurdle criteria Learning outcomes Tutorials (12) 15 Individual Formative Weeks 1-12 1. 2. 3. 4. 5. 6. Mid-semester tests (3) 15 Individual Formative Weeks 4, 7, 10 1. 2. 3. 4. Research assignment 5 Group Formative Week 11 6. 7. Exam 65 Individual Summative Min 40% 1. 2. 3. 4. 5. 6. Total 100
This assessment breakdown is registered as an exemption to the University's Assessment for Coursework Programs Policy. The exemption is related to the Procedures clause(s): 1. b. 3.
This course has a hurdle requirement. Meeting the specified hurdle criteria is a requirement for passing the course.
Due to the current COVID-19 situation modified arrangements have been made to assessments to facilitate remote learning and teaching. Assessment details provided here reflect recent updates.
To support the changes to teaching, the following revisions to assessment have been made:-
We will run Tests 2 and 3 in weeks 7 and 10, respectively, as scheduled before.
Here is part of the latest message form the University regarding the final exam: "... The University will not hold exams as usual this
semester. Instead, all invigilated exams requiring personal attendance will need to be changed to alternative assessments - without invigilation, administered through MyUni. Example alternatives might include open-book exams, online tests, or written reports." Therefore, I will announce the alternative assessment late next week and explain howwe will run it.
Assessment Related RequirementsThe examination is a hurdle requirement. It is necessary to achieve at least 40% in the exam. If this is not achieved, the total course mark will be limited to a maximum of 49. Further details of hurdle requirements are explained in the University's Assessment for Coursework Programs Policy.
Assessment DetailTutorials: students maintain an exercise book in which they record tutorial preparation and the work completed during tutorials. This is assessed during tutorials on the basis of the student having attempted and then corrected prescribed exercises.
Tests: 40 minute tests are held in weeks 4, 7 and 10.
Research Assignment: students work in a small group to write short report on an emerging electronic technology. Groups are assigned a member of staff to advise them on their topic. The report should draw upon research published in high-quality sources. It is due in week 11.
Exam: a 2-hour examination is held at the end of the semester.
SubmissionTutorial preparation and tutorial exercises are marked during the tutorial sessions with verbal feedback given immediately. In Tutorial 3, for example, the exercises for Tutorial 2 and the preparation for Tutorial 3 are marked.
Students can expect the marks from their continuous assessment activities to be available on MyUni within two weeks of the activity.
The report for the research assignment is due in week 9 and will be submitted on MyUni (and may use TurnItIn).
In keeping with the University’s policy on Modified Arrangements for Coursework Assessment, students whose capacity to demonstrate their true level of competence in a continuous assessment task was seriously impaired because of approved medical, compassionate or extenuating circumstances will be offered the following modified arrangements.
- For tutorials: an extension of the deadline.
- For a test: by excluding the assessment in question and proportionally scaling up the student’s marks for work completed during the course.
- For the research assignment: an extension of the deadline.
Grades for your performance in this course will be awarded in accordance with the following scheme:
M10 (Coursework Mark Scheme) Grade Mark Description FNS Fail No Submission F 1-49 Fail P 50-64 Pass C 65-74 Credit D 75-84 Distinction HD 85-100 High Distinction CN Continuing NFE No Formal Examination RP Result Pending
Further details of the grades/results can be obtained from Examinations.
Grade Descriptors are available which provide a general guide to the standard of work that is expected at each grade level. More information at Assessment for Coursework Programs.
Final results for this course will be made available through Access Adelaide.
The University places a high priority on approaches to learning and teaching that enhance the student experience. Feedback is sought from students in a variety of ways including on-going engagement with staff, the use of online discussion boards and the use of Student Experience of Learning and Teaching (SELT) surveys as well as GOS surveys and Program reviews.
SELTs are an important source of information to inform individual teaching practice, decisions about teaching duties, and course and program curriculum design. They enable the University to assess how effectively its learning environments and teaching practices facilitate student engagement and learning outcomes. Under the current SELT Policy (http://www.adelaide.edu.au/policies/101/) course SELTs are mandated and must be conducted at the conclusion of each term/semester/trimester for every course offering. Feedback on issues raised through course SELT surveys is made available to enrolled students through various resources (e.g. MyUni). In addition aggregated course SELT data is available.
The following changes have been made for 2019 in response to last year's feedback
- created more space at end of course
- reorganised tutorials a bit
- moved research assignment forward
- added Q&A workshops
- refreshed content
- upgraded lab hardware
- migrated from Verilog to SystemVerilog
- software now in CATS
- relocated tutorials to CATS
- created more space at end of course
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This section contains links to relevant assessment-related policies and guidelines - all university policies.
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