ELEC ENG 2100 - Digital Systems

North Terrace Campus - Semester 2 - 2024

This course develops engineering capabilities pertaining to the design of digital electronic systems. Designs for contemporary implementation technologies are expressed using circuit schematics and SystemVerilog, at levels of abstraction from CMOS transistor circuits up to processor microarchitecture. System architecture, microarchitecture and interfacing concepts are developed through an extended case study of a commercial microprocessor. The course operates as a flipped classroom with students attending weekly 2-hour workshops. Preparatory lectures, reading and exercise questions are completed before workshops. Workshop problems are more open-ended and typically require discussion in small groups, practical design, simulation and implementation using computers and reconfigurable logic circuits.

  • General Course Information
    Course Details
    Course Code ELEC ENG 2100
    Course Digital Systems
    Coordinating Unit Electrical and Electronic Engineering
    Term Semester 2
    Level Undergraduate
    Location/s North Terrace Campus
    Units 3
    Contact Typically up to 2 hours per week but up to 5 hours in the weeks with practicals
    Available for Study Abroad and Exchange Y
    Prerequisites ELEC ENG 1102
    Incompatible ELEC ENG 3028
    Course Description This course develops engineering capabilities pertaining to the design of digital electronic systems. Designs for contemporary implementation technologies are expressed using circuit schematics and SystemVerilog, at levels of abstraction from CMOS transistor circuits up to processor microarchitecture. System architecture, microarchitecture and interfacing concepts are developed through an extended case study of a commercial microprocessor. The course operates as a flipped classroom with students attending weekly 2-hour workshops. Preparatory lectures, reading and exercise questions are completed before workshops. Workshop problems are more open-ended and typically require discussion in small groups, practical design, simulation and implementation using computers and reconfigurable logic circuits.
    Course Staff

    Course Coordinator: Associate Professor Braden Phillips

    Course Timetable

    The full timetable of all activities for this course can be accessed from Course Planner.

  • Learning Outcomes
    Course Learning Outcomes
    On successful completion of this course students will be able to:
    1 Design, build and test digital logic for systems of moderate complexity using common digital components, schematic diagrams, and hardware description language
    2 Use and explain engineering practices to manage the complexity of digital systems
    3 Use appropriate implementation technologies for digital systems
    4 Design CMOS logic gates at the transistor schematic level
    5 Work effectively and ethically in teams to undertake the design of digital systems

     
    The above course learning outcomes are aligned with the Engineers Australia Entry to Practice Competency Standard for the Professional Engineer. The course develops the following EA Elements of Competency to levels of introductory (A), intermediate (B), advanced (C):  
     
    1.11.21.31.41.51.62.12.22.32.43.13.23.33.43.53.6
    B C C A B B C B B B B B B
    University Graduate Attributes

    This course will provide students with an opportunity to develop the Graduate Attribute(s) specified below:

    University Graduate Attribute Course Learning Outcome(s)

    Attribute 1: Deep discipline knowledge and intellectual breadth

    Graduates have comprehensive knowledge and understanding of their subject area, the ability to engage with different traditions of thought, and the ability to apply their knowledge in practice including in multi-disciplinary or multi-professional contexts.

    1-5

    Attribute 2: Creative and critical thinking, and problem solving

    Graduates are effective problems-solvers, able to apply critical, creative and evidence-based thinking to conceive innovative responses to future challenges.

    1-5

    Attribute 3: Teamwork and communication skills

    Graduates convey ideas and information effectively to a range of audiences for a variety of purposes and contribute in a positive and collaborative manner to achieving common goals.

    2, 5

    Attribute 4: Professionalism and leadership readiness

    Graduates engage in professional behaviour and have the potential to be entrepreneurial and take leadership roles in their chosen occupations or careers and communities.

    2, 5

    Attribute 5: Intercultural and ethical competency

    Graduates are responsible and effective global citizens whose personal values and practices are consistent with their roles as responsible members of society.

    5

    Attribute 7: Digital capabilities

    Graduates are well prepared for living, learning and working in a digital society.

    1-5

    Attribute 8: Self-awareness and emotional intelligence

    Graduates are self-aware and reflective; they are flexible and resilient and have the capacity to accept and give constructive feedback; they act with integrity and take responsibility for their actions.

    5
  • Learning Resources
    Required Resources
    Textbook: David Harris and Sarah Harris, Digital Design and Computer Architecture, Elsevier, Second Edition (2013). The full text of this book is available electronically from the University of Adelaide Library.

    A set of slides, recorded slide show presentations, practice problems, worked solutions, and other supporting materials will be available for downloading from the course web site. 
    Online Learning
    This course uses the MyUni web site. All announcements are posted on MyUni. Recorded slide show presentations, practice and tutorial questions, and other resources are available on MyUni. The gradebook is used to communicate marks. The research assignment is submitted using MyUni. A discussion board is available for course-related discussion.
  • Learning & Teaching Activities
    Learning & Teaching Modes
    Workshops: the course uses a flipped classroom with an emphasis on weekly 3-hour face-to-face workshops. Students prepare for workshops by reading sections of the textbook, watching recorded presentations, and attempting preparation exercises. During workshops, teaching staff spend time with each student individually to help explain difficult concepts. Workshop time is also spent working as individuals on exercise problems and in small groups on design problems.

    Recorded Presentations: wherever possible the presentations follow the structure, terminology and notation of the course textbook. Slides and recoded presentations are available prior to workshops and, where material outside of the scope of the textbook is presented, detailed notes are provided. Students are expected to read sections of the textbook, watch the presentations and attempt some exercise problems in preparation for workshops.
    Workload

    The information below is provided as a guide to assist students in engaging appropriately with the course requirements.

    The information below is provided as a guide to help students engage appropriately with the course requirements.

    Activity Contact Hours Workload Hours
    Workshop Preparation 36
    Recorded Slide Presentaions 36
    Tests 3 12
    Workshops (2 hrs / 3 hr session) 36 36
    Assignment 6
    Practice Questions and Revision 24
    Total 39 150


    Learning Activities Summary
    Week Workshop Topic Test
    1 Topic 1: Building Digital Systems
    2 Topic 1: Building Digital Systems
    3 Topic 2: Combinational Logic Design
    4 Topic 2: Combinational Logic Design Test 1
    5 Topic 3: Sequential Logic Design
    6 Topic 3: Sequential Logic Design
    7 Topic 4: CMOS Logic Test 2
    8 Topic 4: CMOS Logic
    9 Topic 5: Digital Subsystems & Interfaces
    10 Topic 5: Digital Subsystems & Interfaces Test 3
    11 Review and Integration
    12 Review and Integration
  • Assessment

    The University's policy on Assessment for Coursework Programs is based on the following four principles:

    1. Assessment must encourage and reinforce learning.
    2. Assessment must enable robust and fair judgements about student performance.
    3. Assessment practices must be fair and equitable to students and give them the opportunity to demonstrate what they have learned.
    4. Assessment must maintain academic standards.

    Assessment Summary
    Assessment Task Weighting (%) Individual/ Group Formative/ Summative
    Due (week)*
    Learning outcomes
    Workshops (12) 12 Individual Formative Weeks 1-12 1-5
    Mid-semester tests (3) 24 Individual Summative Weeks 4, 7, 10 1-4
    Assignment 8 Individual Summative Week 9 1-4
    Exam 56 Individual Summative 1-4
    Total 100
    * The specific due date for each assessment task will be available on MyUni.
     
    This assessment breakdown is registered as an exemption to the University's Assessment for Coursework Programs Policy. The exemption is related to the Procedures clause(s): 1. b. 3.
    Assessment Detail
    Workshops: students maintain an exercise book in which they record tutorial preparation and the work completed during tutorials. This is assessed during tutorials on the basis of the student having attempted and then corrected prescribed exercises.

    Tests: 60-minute tests are held online in weeks 4, 7 and 10.

    Exam: a 2-hour examination is held at the end of the semester.

    Assignment: an individual SystemVerilog assignment.
    Submission
    Workshops: logbooks are marked during the workshops. Marks are awarded for completion of the previous workshop and preparation for the current one.

    Tests: test are completed online in MyUni during the scheduled hour shown in Access Adelaide for weeks 4, 7, and 10.

    Assignment: the assignment is required to be submitted online with the SystemVerilog code and a short video to demonstrate the functionality of the program.

    Exam: the exam is conduced as part of the University scheduled and facilitated exams at the end of semster.

    Extensions for workshops and tests can be arranged for circumstances eligible for modified arranegments under the Modified Arrangements for Coursework Assessment Policy. Please contact the Course Coordinator or to request an extension.
    Course Grading

    Grades for your performance in this course will be awarded in accordance with the following scheme:

    M10 (Coursework Mark Scheme)
    Grade Mark Description
    FNS   Fail No Submission
    F 1-49 Fail
    P 50-64 Pass
    C 65-74 Credit
    D 75-84 Distinction
    HD 85-100 High Distinction
    CN   Continuing
    NFE   No Formal Examination
    RP   Result Pending

    Further details of the grades/results can be obtained from Examinations.

    Grade Descriptors are available which provide a general guide to the standard of work that is expected at each grade level. More information at Assessment for Coursework Programs.

    Final results for this course will be made available through Access Adelaide.

  • Student Feedback

    The University places a high priority on approaches to learning and teaching that enhance the student experience. Feedback is sought from students in a variety of ways including on-going engagement with staff, the use of online discussion boards and the use of Student Experience of Learning and Teaching (SELT) surveys as well as GOS surveys and Program reviews.

    SELTs are an important source of information to inform individual teaching practice, decisions about teaching duties, and course and program curriculum design. They enable the University to assess how effectively its learning environments and teaching practices facilitate student engagement and learning outcomes. Under the current SELT Policy (http://www.adelaide.edu.au/policies/101/) course SELTs are mandated and must be conducted at the conclusion of each term/semester/trimester for every course offering. Feedback on issues raised through course SELT surveys is made available to enrolled students through various resources (e.g. MyUni). In addition aggregated course SELT data is available.

    The following changes have been made for 2024 in response to last year's feedback

    • changed one of the workshops to be a special SystemVerilog review
    • the activities of one of the workshops, which have typically taken much longer than the others, will be submitted as an assignment so that it receives extra weight in the assessment. The exam weight has been reduced.
    • reduced the focus of SystemVerilog assessment in the tests, given it will be covered in the new assignment.
    • moved to 3-hour flexible workshops.
  • Student Support
  • Policies & Guidelines
  • Fraud Awareness

    Students are reminded that in order to maintain the academic integrity of all programs and courses, the university has a zero-tolerance approach to students offering money or significant value goods or services to any staff member who is involved in their teaching or assessment. Students offering lecturers or tutors or professional staff anything more than a small token of appreciation is totally unacceptable, in any circumstances. Staff members are obliged to report all such incidents to their supervisor/manager, who will refer them for action under the university's student’s disciplinary procedures.

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