ELEC ENG 4109 - Digital Microelectronics
North Terrace Campus - Semester 1 - 2020
General Course Information
Course Code ELEC ENG 4109 Course Digital Microelectronics Coordinating Unit School of Electrical & Electronic Engineering Term Semester 1 Level Undergraduate Location/s North Terrace Campus Units 3 Contact Up to 4 hours per week Available for Study Abroad and Exchange Y Prerequisites ELEC ENG 2101 Incompatible ELEC ENG 3109, ELEC ENG 4053 Assumed Knowledge ELEC ENG 2100 Course Description This course examines the design and technologies underlying modern digital microelectronic systems. The list of topics include: Introduction to fabrication processes; Design rules (revisited); Transistor models (revisited from second year electronics); Layout issues; ASIC design flow; VLSI design methodology and leaf cell design; Performance estimation of CMOS complex gates and interconnected modules using logical effort; Interconnect types and issues, clock distribution, design margin, reliability and scaling; Static and dynamic CMOS logic families and adders design; Memories-static and dynamic RAMS, Pseudo-NMOS and dynamic PLA; Low power design and system level consideration. Assessments include tests, computer labs and a final examination.
Course Coordinator: Dr Said Al-SarawiCourse Coordinator and Lecturer: Dr Said Al-Sarawi
Office: Ingkarni Wardli 3.39
The full timetable of all activities for this course can be accessed from Course Planner.
Course Learning OutcomesOn successful completion of this course students will be able to:
- Explain CMOS technology fabrication and device characteristics and parasitic effects
- Design digital logic gates and standard cells at transistor schematic and corresponding layouts level in CMOS technology using CMOS logic gates, pseudo-nMOS, footed and footless domino logic families.
- Explain and evaluate the effect of the parasitic and loading on CMOS circuit operation and performance in terms of size, area and noise margin and ways to minimise delay.
- Model the effect of interconnect upon a design and to apply strategies to mitigate problems arising from interconnect loading.
- Explain the function of CMOS memory circuits and design basic CMOS ROM and PLA circuits.
- Explain factors that influence circuit reliability and be able to apply reasonable design margins.
- Explain the effect of scaling on circuit behaviour and appreciate technology trends with respect to scaling.
- Explain system level considerations such as floor planning, power dissipation, clock skew and micro-architecture to system performance.
- Use a set of software tools to specify, synthesise, layout and simulate microelectronic circuits.
- Demonstrate team work to design a system module
The above course learning outcomes are aligned with the Engineers Australia Stage 1 Competency Standard for the Professional Engineer.
The course is designed to develop the following Elements of Competency: 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 3.1 3.2 3.3 3.4 3.5 3.6
University Graduate Attributes
This course will provide students with an opportunity to develop the Graduate Attribute(s) specified below:
University Graduate Attribute Course Learning Outcome(s) Deep discipline knowledge
- informed and infused by cutting edge research, scaffolded throughout their program of studies
- acquired from personal interaction with research active educators, from year 1
- accredited or validated against national or international standards (for relevant programs)
1,4,6,7,8 Critical thinking and problem solving
- steeped in research methods and rigor
- based on empirical evidence and the scientific approach to knowledge development
- demonstrated through appropriate and relevant assessment
2,3,5,8 Teamwork and communication skills
- developed from, with, and via the SGDE
- honed through assessment and practice throughout the program of studies
- encouraged and valued in all aspects of learning
9-10 Career and leadership readiness
- technology savvy
- professional and, where relevant, fully accredited
- forward thinking and well informed
- tested and validated by work based experiences
2,6,9,10 Intercultural and ethical competency
- adept at operating in other cultures
- comfortable with different nationalities and social contexts
- able to determine and contribute to desirable social outcomes
- demonstrated by study abroad or with an understanding of indigenous knowledges
10 Self-awareness and emotional intelligence
- a capacity for self-reflection and a willingness to engage in self-appraisal
- open to objective and constructive feedback from supervisors and peers
- able to negotiate difficult social situations, defuse conflict and engage positively in purposeful debate
Neil H. E. Weste & David Harris, “CMOS VLSI design: a circuits and systems perspective,” Addison Wesley, 3rd edition, 2004.
Rabaey, Chandrakasan & Nikolil, “Digital Integrated Circuits,” Prentice Hall, 2nd edition, 2003.
A set of course notes, practice problems and other supporting materials will also be available for downloading from the course web site.
Online LearningExtensive use will be made of the MyUni Website (Canvas Learning Management System) for this course,
Course notes, tutorial problems and solutions, laboratory exercises and practice problems will all be available for downloading from the Website. Where the lecture theatre facilities permit, audio or video recordings of lectures will also be available for downloading.
Learning & Teaching Activities
Learning & Teaching ModesThis course relies on lectures as the primary delivery mechanism for the material. Tutorials are provided as supplement for the lectures materials. These tutorials provide exercises and example problems to enhance the understanding obtained throughout lectures. Practicals are used to provide hands-on experience using industry standard computer aided design (CAD) tools called Cadence. These practicals will help reinforce the theoretical concepts encountered in lectures. Continuous assessment activities provide formative assessment opportunities for students to gauge their progress and understanding.
The information below is provided as a guide to assist students in engaging appropriately with the course requirements.
The information below is provided as a guide to assist students in engaging appropriately with the course requirements.
Activity Contact Hours Workload Hours Lecture 24 Lectures 24 48 Tutorials 6 Tutorials 6 12 Practicals Computer Lab 1 3 3 Computer Lab 2 3 6 Computer Lab 3 4 12 Computer Lab 4 6 24 Test Theory part of the course 1 6 Exam All Theory Part 2 30 Total 51 141
Learning Activities Summary
Lectures Activity Session No. Week No of Lectures Introduction to the course and presentation of prac structure 1&2 1 2 Introduction to fabrication processes, design rules (revisted). Transistor models (revisited from third year electronics) and layout issues and ASIC design flow 2&3 2 2 VLSI design methodology and leaf cell design 4&5 3 2 Performance estimation of CMOS complex gates and interconnected modules using logical effort 6-13 4-7 8 Interconnect issues, clock distribution, design margin, reliability and scaling 14-17 8,9 4 Static and dynamic CMOS logic families and adders design 18,19,20 10,11 2 Memory structures and operation 21,22 11,12 2 Low power design and system level consideration 23-24 12 2 Tutorials Activity Sessions Week Topic Demonstrating the design of CMOS gates and transistor sizing 1 2 Tutorial 1 CMOS circuits layout and delay estimation 2 4 Tutorial 2 CMOS circuits delay estimation using logical effort 3 6 Tutorial 3 Delay path estimation using logical effort 4 8 Tutorial 4 Delay and crosstalk in interconnects 5 10 Tutorial 5 PLA and memory Design 6 12 Tutorial 6
Note that practical classes begin in week 1 of the semester and run in odd weeks. Students must attend their allocated practical class, when further instructions on the operation of the laboratory session will be provided. Students should be aware of the Occupational Health and Safety issues associated with working in a laboratory environment.
The University's policy on Assessment for Coursework Programs is based on the following four principles:
- Assessment must encourage and reinforce learning.
- Assessment must enable robust and fair judgements about student performance.
- Assessment practices must be fair and equitable to students and give them the opportunity to demonstrate what they have learned.
- Assessment must maintain academic standards.
Assessment Task Weighting (%) Individual/ Group Formative/ Summative Due (week)* Hurdle criteria Learning outcomes Computer Lab 1 2 Individual Diagnostic Weeks 1-3 2. 3. 9. Computer Lab 2 3 Individual Diagnostic Weeks 4-6 2. 3. 9. Computer Lab3 5 Individual Diagnostic Weeks 7-8 2. 3. 4. 9. Computer Lab 4 15 Group Summative Weeks 9-13 2. 3. 4. 5. 8. 9. 10. Test 10 Individual Summative Week 10 1. 2. 3. 4. 5. 6. 7. 8. Exam 65 Individual Summative Week 14 Min 40% 1. 2. 3. 4. 5. 6. 7. 8. Total 100
This assessment breakdown complies with the University's Assessment for Coursework Programs Policy.
This course has a hurdle requirement. Meeting the specified hurdle criteria is a requirement for passing the course.
Due to the current COVID-19 situation modified arrangements have been made to assessments to facilitate remote learning and teaching. Assessment details provided here reflect recent updates.
Exam - 55% weighting (decreased from 65%)
Tutorials - 10% weighting (increased from no credit)
Tests - 10% weighting (same)
Practricals - 25% weighting (same)
Starting from this week, tutorials will be assessed and will be worth 10% of the total assessment. The rationale behind this
change is to reduce the weighing of the final Exam by 10% and use that as a continuous assessment. This update should reduce the pressure that some students my face when it come the final exam for both courses.
Because we will be using a new software called Electric, we need to build our experience with the schematic editor and
layout editors then simulation, so we need to start from Computer Prac
1. If you have finished that using Cadence and had that marked, then that mark can be taken, if not then this Prac 1 has to be done in Electric software. If a student who already received a mark a Prac 1 and wants to do it in Electric, this can be accommodate and the best of these two marks will be counted. Further, it would be much easier to support Electric using Zoom Q&A sessions during the allocated practical times.
The test assessment will run online. A number of questions will be provided to you on MyUni and you will be required to provide an online answers to these questions, some of these might be numerical or require working, so you will also be required to submit
your working by taking an image of your work and do the submission online. Please get used for this form of interaction.
The weighting for final exam for undergraduate course will drop from 65% of the total assessment to 55%. For the postgraduate
students, this will be drop from 55% to 45% of the total assessment. The difference is pushed to the continuous assessment part of the course, in this case it is the tutorials. Again, similar to the test, students will be required to submit scanned copies of their worked solutions during a timed session. The details for that will be provided in due date.
Assessment DetailThe examination is a hurdle requirement. It is necessary to achieve at least 40% of the exam makr. If this is not achieved, the total course mark will be limited to a maximum of 49.
A hurdle requirement is defined by the University's Assessment for Coursework Programs policy as "...an assessment task mandating a minimum level of performance as a condition of passing the course.If a student fails to meet a hurdle requirement (normally no less than 40%),and is assigned a total mark for the course in the range of 45-49, then the student is entitled to an offer of additional assessment of some type. The type of assessment is to be decided by the School Assessment Review Committee when determining final results. The student’s final total mark will be entered at no more than 49% and the offer of an additional assessment will be specified eg. US01. Once the additional assessment has been completed, this mark will be included in the calculation of the total mark for the course and the better of the two results will apply. Note however that the maximum final result for a course in which a student has sat an additional assessment will be a “50 Pass”.
If a student is unable to meet a hurdle requirement related to an assessment piece (may be throughout semester or at semester’s end) due to medical or compassionate circumstances beyond their control, then the student is entitled to an offer of replacement assessment of some type. An interim result of RP will be entered for the student, and the student will be notified of the offer of a replacement assessment. Once the replacement assessment has been completed, the result of that assessment will be included in the calculation of the total mark for the course.An assessment of work done during the lab will be conducted at the end of each lab session.
SubmissionThere is no submission of assignment needed for this course. Each Computer Lab activity will be assessed during the laboratory session allocated. In case, times run out during the session, the assessment will be done in the following computer laboratory session, unless it is the final session. In this case all computer laboratory assignments have to be finalised within that session.
Grades for your performance in this course will be awarded in accordance with the following scheme:
M10 (Coursework Mark Scheme) Grade Mark Description FNS Fail No Submission F 1-49 Fail P 50-64 Pass C 65-74 Credit D 75-84 Distinction HD 85-100 High Distinction CN Continuing NFE No Formal Examination RP Result Pending
Further details of the grades/results can be obtained from Examinations.
Grade Descriptors are available which provide a general guide to the standard of work that is expected at each grade level. More information at Assessment for Coursework Programs.
Final results for this course will be made available through Access Adelaide.
The University places a high priority on approaches to learning and teaching that enhance the student experience. Feedback is sought from students in a variety of ways including on-going engagement with staff, the use of online discussion boards and the use of Student Experience of Learning and Teaching (SELT) surveys as well as GOS surveys and Program reviews.
SELTs are an important source of information to inform individual teaching practice, decisions about teaching duties, and course and program curriculum design. They enable the University to assess how effectively its learning environments and teaching practices facilitate student engagement and learning outcomes. Under the current SELT Policy (http://www.adelaide.edu.au/policies/101/) course SELTs are mandated and must be conducted at the conclusion of each term/semester/trimester for every course offering. Feedback on issues raised through course SELT surveys is made available to enrolled students through various resources (e.g. MyUni). In addition aggregated course SELT data is available.
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This section contains links to relevant assessment-related policies and guidelines - all university policies.
- Academic Credit Arrangement Policy
- Academic Honesty Policy
- Academic Progress by Coursework Students Policy
- Assessment for Coursework Programs
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- Student Experience of Learning and Teaching Policy
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